CPC G06F 13/1668 (2013.01) [G06F 9/4881 (2013.01); G06F 11/076 (2013.01); G06F 11/3037 (2013.01); G06F 11/3058 (2013.01); G06F 13/1605 (2013.01)] | 14 Claims |
1. A memory controller comprising:
an interface through which the memory controller communicates with an external nonvolatile memory including a plurality of memory chips; and
a channel arbitration circuit configured to manage a plurality of channels via which the memory controller communicates with the external nonvolatile memory,
wherein the channel arbitration circuit is configured to check an operation status of each of the plurality of memory chips of the external nonvolatile memory, and to manage the plurality of channels based on the operation status and information about power consumption for each of a plurality of operations,
wherein the channel arbitration circuit is configured to predict overall power consumption for the plurality of operations based on an operation type of each of the plurality of operations indicated by the operation status of each of the memory chips and an amount of power consumed by the corresponding operation type,
when the channel arbitration circuit predicts that the overall power consumption is greater than a first amount, the channel arbitration circuit defers transmission of a first command received from an external host, and when the channel arbitration circuit predicts that the overall power consumption is not greater than the first amount, the channel arbitration circuit transmits the first command.
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