	US 12,013,791 B2
	Reset dynamic address translation protection instruction
Bruce Conrad Giamei, Lagrangeville, NY (US); Timothy Slegel, Staatsburg, NY (US); Christian Borntraeger, Stuttgart (DE); Damian Osisek, Vestal, NY (US); Lisa Cranton Heller, Rhinebeck, NY (US); Ute Gaertner, Schoenaich (DE); Christine Michele Yost, Hopewell Junction, NY (US); and Elpida Tzortzatos, Lagrangeville, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Jun. 1, 2021, as Appl. No. 17/335,224.
Prior Publication US 2022/0382682 A1, Dec. 1, 2022
Int. Cl. G06F 12/1027 (2016.01); G06F 12/02 (2006.01); G06F 12/0891 (2016.01); G06F 12/14 (2006.01)

CPC G06F 12/1027 (2013.01) [G06F 12/0246 (2013.01); G06F 12/0292 (2013.01); G06F 12/0891 (2013.01); G06F 12/1425 (2013.01)]

22 Claims

1. A computer program product for facilitating processing within a computing environment, the computer program product comprising:

at least one computer-readable storage medium having program instructions embodied therewith, the program instructions being readable by a processor to cause the processor to perform a method comprising:

receiving, at the processor, from an operating system of the computing environment a reset dynamic address translation protection instruction with an operation code field indicating a reset address translation protection operation is to be performed, the reset dynamic address translation protection instruction being part of an instruction set architecture, and being a single instruction issued by the operating system, and being received, by the processor, based on an application executing on the processor encountering an address translation protection bit exception due to a write access to a storage block being blocked by an address translation protection bit in a specified translation table entry associated with the storage block, the translation table entry being in a translation lookaside buffer cache at the processor;

executing the reset dynamic address translation protection instruction, by the processor, to perform the reset address translation protection operation, the executing the reset dynamic address translation protection instruction comprising:

determining, by the processor, that the address translation protection bit in the specified translation table entry associated with the storage block in the translation lookaside buffer cache at the processor is to be reset;

based on the determining, resetting the address translation protection bit to deactivate write protection for the storage block, the resetting being regardless of any associated action by one or more other processors of the computing environment;

clearing any translation lookaside buffer entries in the processor associated with the specified translation table entry; and

wherein the determining, resetting and clearing are performed as part of executing the single reset dynamic address translation protection instruction.