US 12,013,790 B2
Unified address translation for virtualization of input/output devices
Utkarsh Y. Kakaiya, El Dorado Hills, CA (US); Sanjay Kumar, Hillsboro, OR (US); Rajesh M. Sankaran, Portland, OR (US); Philip R. Lantz, Cornelius, OR (US); Ashok Raj, Portland, OR (US); and Kun Tian, Shanghai (CN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 22, 2023, as Appl. No. 18/321,490.
Application 18/321,490 is a continuation of application No. 16/651,786, granted, now 11,698,866, previously published as PCT/US2017/068938, filed on Dec. 29, 2017.
Prior Publication US 2023/0418762 A1, Dec. 28, 2023
Int. Cl. G06F 12/1009 (2016.01); G06F 9/455 (2018.01); G06F 12/06 (2006.01); G06F 12/1081 (2016.01)
CPC G06F 12/1009 (2013.01) [G06F 9/45558 (2013.01); G06F 12/063 (2013.01); G06F 12/1081 (2013.01); G06F 2009/45579 (2013.01); G06F 2009/45583 (2013.01); G06F 2009/45591 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A method comprising:
creating, for a virtual machine (VM) by a virtual machine monitor (VMM), a virtual input/output memory management unit (IOMMU) corresponding to a physical IOMMU, the virtual IOMMU having a process address space identifier (PASID) entry width that is smaller than the PASID entry width of the physical IOMMU; and
shadowing, by the VMM, a guest PASID from the virtual IOMMU in the physical IOMMU.