US 12,013,789 B2
Flexible information compression at a memory system
Yanming Liu, Shanghai (CN); Zhenzhen Yang, Shanghai (CN); Yi Heng Sun, Shanghai (CN); and Junjun Wang, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 22, 2021, as Appl. No. 17/645,686.
Prior Publication US 2023/0195646 A1, Jun. 22, 2023
Int. Cl. G06F 12/1009 (2016.01)
CPC G06F 12/1009 (2013.01) [G06F 2212/7201 (2013.01)] 25 Claims
OG exemplary drawing
 
22. A method, comprising:
receiving a first command for accessing a first logical address associated with a memory system;
generating, based at least in part on the first command, a first entry of a change log with first information associated with the first command, the change log associated with a mapping between logical addresses and physical addresses of the memory system;
receiving a second command for accessing a second logical address associated with the memory system, the second command different from the first command, wherein the second logical address is sequentially indexed with the first logical address associated with the first command;
updating, based at least in part on the second logical address, associated with the second command, being sequentially indexed with the first logical address, the first entry of the change log with a first flag indicating that the first logical address is sequentially indexed with the second logical address; and
generating a second entry of the change log with second information associated with the second command, the second entry different than the first entry, and the second entry comprising a second flag indicating that the second logical address is sequentially indexed with the first logical address.