snooping a cache coherent interconnect of a host computer on which the host application is running, wherein the cache coherent interconnect is snooped for dirty cache lines, each dirty cache line having an address; and

writing, only when an address of a dirty cache line has a match in a snapshot address table, data of the dirty cache line to a non-volatile memory, wherein whether the data is written to a buffer in the FPGA before being written to the non-volatile memory or only the address of the dirty cache line, but not the data itself, is written to the buffer, depends on a size of the buffer, how often data of the dirty cache line is snooped, or depends on both the size of the buffer and how often data of the dirty cache line is snooped.