US 12,013,771 B2
Method and interconnect interface for built-in self-test
Chunhui Zheng, Beijing (CN); and Jiao Li, Xi'an (CN)
Assigned to SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD., Shanghai (CN)
Filed by Shanghai Zhaoxin Semiconductor Co., Ltd., Shanghai (CN)
Filed on Apr. 15, 2022, as Appl. No. 17/721,560.
Claims priority of application No. 202111312589.5 (CN), filed on Nov. 8, 2021.
Prior Publication US 2023/0141802 A1, May 11, 2023
Int. Cl. G06F 11/27 (2006.01); G06F 13/40 (2006.01)
CPC G06F 11/27 (2013.01) [G06F 13/4068 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A method for built-in self-test, including:
at a transmitting part, selecting a gold pattern, generating a test pattern using the gold pattern and a header corresponding to the gold pattern, and transmitting the test pattern to a receiving part via a tested path; and
at the receiving part, parsing the header and a received pattern from the test pattern received, obtaining the gold pattern based on the header parsed according to the correspondence between the header and the gold pattern, and obtaining a test result of the tested path by comparing the gold pattern to the received pattern.