US 12,013,754 B2
Nonvolatile memory device and memory system including nonvolatile memory device
Beomkyu Shin, Seongnam-si (KR); and Sungkyu Park, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 20, 2021, as Appl. No. 17/479,067.
Application 17/479,067 is a continuation of application No. 16/506,307, filed on Jul. 9, 2019, granted, now 11,144,388.
Claims priority of application No. 10-2018-0159264 (KR), filed on Dec. 11, 2018.
Prior Publication US 2022/0004457 A1, Jan. 6, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 3/06 (2006.01); G11C 29/52 (2006.01); G11B 20/18 (2006.01); G11C 7/10 (2006.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01); G11C 16/10 (2006.01); G11C 29/42 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 29/52 (2013.01); G06F 3/065 (2013.01); G11B 2020/1823 (2013.01); G11C 7/1006 (2013.01); G11C 11/5628 (2013.01); G11C 13/0069 (2013.01); G11C 16/10 (2013.01); G11C 29/42 (2013.01); G11C 2211/5646 (2013.01); G11C 2211/5647 (2013.01)] 20 Claims
OG exemplary drawing
 
13. A nonvolatile memory device comprising:
a plurality of memory cells;
an inversion circuit configured to receive first write data, and to invert the first write data to generate second write data;
a flag bit adding circuit configured to receive the first write data and the second write data, to add a first flag bit to the second write data to generate third write data including the first flag bit, and to add a second flag bit to the first write data to generate fourth write data including the second flag bit; and
a compare and write circuit configured to receive the third write data including the first flag bit and the fourth write data including the second flag bit, to perform a first comparison between a first read data and the third write data including the first flag bit, to perform a second comparison between the first read data and the fourth write data including the second flag bit, to select one of the third write data including the first flag bit and the fourth write data including the second flag bit based on a result of the first comparison and the second comparison, and to write the selected one of the third write data including the first flag bit and the fourth write data including the second flag bit in the plurality of memory cells,
wherein both the first comparison and the second comparison occur after the flag bit adding circuit outputs both the third write data including the first flag bit and the fourth write data including the second flag bit to the compare and write circuit.