US 12,013,752 B2
Host-level error detection and fault correction
Sudhanva Gurumurthi, Austin, TX (US); and Vilas Sridharan, Boston, MA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Jun. 16, 2022, as Appl. No. 17/841,864.
Prior Publication US 2023/0409426 A1, Dec. 21, 2023
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/1004 (2013.01) [G06F 11/0772 (2013.01); G06F 11/102 (2013.01); G06F 11/1068 (2013.01)] 20 Claims
OG exemplary drawing
 
10. A system, comprising:
a memory; and
a processing device coupled to the memory, the processing device configured to:
based on a check bit indicating a fetch return of a plurality of fetch returns includes a fault, reconstruct the fetch return based on a parity fetch associated with the plurality of fetch returns and based on one or more other fetch returns of the plurality of fetch returns; and
send the reconstructed fetch return to a data fabric communicatively coupled to the processing device.