US 12,013,688 B2
Method and system for lot-tool assignment
Ren-Chyi You, Yilan County (TW); An-Wei Peng, Hsinchu (TW); Chang-Zong Liu, Hsinchu (TW); and Jun-Sheng Yeh, New Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Dec. 6, 2020, as Appl. No. 17/113,056.
Application 17/113,056 is a continuation of application No. 16/222,678, filed on Dec. 17, 2018, granted, now 10,860,008.
Application 16/222,678 is a continuation of application No. 14/871,896, filed on Sep. 30, 2015, granted, now 10,162,340, issued on Dec. 25, 2018.
Prior Publication US 2021/0089012 A1, Mar. 25, 2021
Int. Cl. G05B 19/418 (2006.01)
CPC G05B 19/41865 (2013.01) [G05B 2219/32266 (2013.01); G05B 2219/32271 (2013.01); G05B 2219/45031 (2013.01); Y02P 90/02 (2015.11)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a dispatching system configured to provide dispatching preferences indicating that tools feed back preferences thereof for at least one lot;
a dispatching rule database coupled to the dispatching system, wherein the dispatching system is configured to write the dispatching preferences into the dispatching rule database; and
at least one processor coupled to the dispatching system and at least one memory, wherein computer program code encoded in the at least one memory is executed by the at least one processor to
generate a tool-lot relationship, based on the dispatching preferences, for at least one of the tools, and
cause the at least one of the tools to perform, based on the tool-lot relationship, semiconductor processes on the at least one lot for semiconductor fabrication, the semiconductor processes including: a deposition process, a planarization process, and a lithography process.