US 12,013,617 B2
Liquid crystal display device
Hajime Kimura, Kanagawa (JP)
Assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Kanagawa-ken (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Nov. 3, 2021, as Appl. No. 17/518,001.
Application 13/488,475 is a division of application No. 12/614,926, filed on Nov. 9, 2009, granted, now 8,232,947, issued on Jul. 31, 2013.
Application 17/518,001 is a continuation of application No. 17/116,731, filed on Dec. 9, 2020, granted, now 11,604,391.
Application 17/116,731 is a continuation of application No. 16/519,110, filed on Jul. 23, 2019, granted, now 10,901,283, issued on Jan. 26, 2021.
Application 16/519,110 is a continuation of application No. 15/668,737, filed on Aug. 4, 2017, granted, now 10,416,517, issued on Jul. 17, 2019.
Application 15/668,737 is a continuation of application No. 13/488,475, filed on Jun. 5, 2012, abandoned.
Claims priority of application No. 2008-292197 (JP), filed on Nov. 14, 2008.
Prior Publication US 2022/0057684 A1, Feb. 24, 2022
Int. Cl. G09G 3/32 (2016.01); G02F 1/1335 (2006.01); G02F 1/1362 (2006.01); G09G 3/20 (2006.01); G09G 3/3233 (2016.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01); H10K 10/46 (2023.01); G02F 1/13363 (2006.01); H10K 10/20 (2023.01)
CPC G02F 1/136286 (2013.01) [G02F 1/133528 (2013.01); G09G 3/20 (2013.01); G09G 3/3233 (2013.01); G09G 3/3677 (2013.01); G11C 19/28 (2013.01); H10K 10/482 (2023.02); G02F 1/133638 (2021.01); G09G 2300/0408 (2013.01); G09G 2300/0417 (2013.01); G09G 2300/0847 (2013.01); G09G 2310/0254 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/08 (2013.01); G09G 2320/043 (2013.01); H10K 10/20 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;
a second circuit in a previous stage of the first circuit; and
a third circuit in a subsequent stage of the first circuit,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein a clock signal is input to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, the second circuit, and the third circuit,
wherein one of a source and a drain of the third transistor and one of a source and a drain of the eighth transistor are electrically connected to a pixel,
wherein the other of the source and the drain of the third transistor is electrically connected to a fourth wiring,
wherein one of a source and a drain of the fifth transistor and one of a source and a drain of the sixth transistor are electrically connected to a third wiring,
wherein a gate of the second transistor is electrically connected to a gate of the fifth transistor, the other of the source and the drain of the sixth transistor, and one of a source and a drain of the ninth transistor,
wherein a gate of the seventh transistor is electrically connected to a fifth wiring,
wherein a first signal is input to the fifth wiring from the third circuit,
wherein a gate of the fourth transistor is electrically connected to a second wiring,
wherein a second signal is input to the second wiring from the second circuit,
wherein one of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the fifth transistor, one of a source and a drain of the seventh transistor, and a gate of the first transistor,
wherein a gate of the ninth transistor is directly connected to one of a source and a drain of the tenth transistor, and
wherein the gate of the ninth transistor is directly connected to one of a source and a drain of the eleventh transistor.