US 12,013,442 B2
In-line detection of electrical fails on integrated circuits
Enlan Yuan, Portland, OR (US); David Sanchez, Portland, OR (US); Amit Paliwal, Hillsboro, OR (US); Manish Sharma, Portland, OR (US); Sairam Subramanian, Portland, OR (US); and Sagar Suthram, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 28, 2018, as Appl. No. 16/147,564.
Prior Publication US 2020/0103451 A1, Apr. 2, 2020
Int. Cl. H01L 21/66 (2006.01); G01R 31/28 (2006.01); G01R 31/307 (2006.01); G01R 31/50 (2020.01); H01L 27/02 (2006.01)
CPC G01R 31/50 (2020.01) [G01R 31/2853 (2013.01); G01R 31/2884 (2013.01); G01R 31/307 (2013.01); H01L 22/32 (2013.01); H01L 22/34 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An apparatus including a device region with one or more integrated circuits and a test region for in-line failure detection of the one or more integrated circuits using an in-line voltage contrast test, the apparatus comprising:
a substrate including a first area for the device region and a second different area for the test region;
a gate layer formed over both of the areas, wherein a first section of the gate layer is formed over the first area and a second section of the gate layer is formed over the second area;
one or more metal layers formed over both of the areas, the one or more metal layers including an upper metal layer having first and second sections formed above the first and second sections of the gate layer, respectively;
wherein the one or more integrated circuits are formed from the first sections of the layers; and
wherein the second section of the upper metal layer is segmented into a set of test segments, wherein a predetermined subset of the set of test segments includes first test segments shorted to the substrate and/or the second section of the gate layer, all of the first test segments of the predetermined subset to appear bright during the in-line voltage contrast test, each remaining second test segment of the set of test segments to selectively appear bright, or dark, respectively depending on whether the remaining second test segment of the set of test segments corresponds to, or does not correspond to, a short defect that shorts the remaining second test segment to the substrate and/or the second section of the gate layer;
wherein the set of test segments include a pair of test segments separated by a dielectric plug, the pair including a non-floating test segment of the first test segments and another test segment of the remaining second test segments;
wherein the non-floating test segment of the pair is electrically connected to a fin of the test region independently of the other test segment of the pair, the fin adjacent to a dummy fin electrically isolated from the fin, and the other test segment of the pair is either:
a floating test segment, or
electrically connected to the non-floating test segment of the pair, only if the dielectric plug is defective, and
said other test segment of the pair to appear bright only if the dielectric plug is defective and otherwise to appear dark.