US 12,336,443 B2
Resistive random access memory and method for manufacturing the same
Chi-Ching Liu, Taichung (TW); Chih-Chao Huang, Taichung (TW); and Shih-Ning Tsai, Taichung (TW)
Assigned to WINBOND ELECTRONICS CORP., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Jan. 7, 2022, as Appl. No. 17/571,149.
Prior Publication US 2023/0225228 A1, Jul. 13, 2023
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01)
CPC H10N 70/8418 (2023.02) [H10B 63/30 (2023.02); H10B 63/80 (2023.02); H10N 70/063 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A method for manufacturing a resistive random access memory, comprising:
forming a conductive line structure in an array area and a periphery circuit area, respectively, wherein the conductive line comprises one or more layers of conductive lines extending horizontally and is free of vias or plugs extending vertically, wherein the formation of the conductive line structure comprises:
forming a lower conductive layer; and
forming an adhesion layer on the lower conductive layer, wherein forming the lower conductive layer and the adhesion layer comprises:
sequentially forming a lower conductive material layer and an adhesion material layer;
forming a patterned mask over the lower conductive layer and the adhesion material layer; and
etching the adhesion material layer and the lower conductive material layer with the patterned mask to form the adhesion layer and the lower conductive layer, respectively;
depositing a dielectric layer to cover the patterned mask;
planarizing the dielectric layer to expose the patterned mask;
removing the patterned mask to form a trench, wherein the trench exposes the adhesion layer; and
forming a memory unit on the conductive line structure in the array area, wherein the forming the memory unit comprises:
forming a lower electrode on the conductive line structure;
forming a resistive switching layer on the lower electrode; and
forming an upper electrode on the resistive switching layer,
wherein the lower electrode of the memory unit is formed directly on an upper surface of the conductive line structure.