US 12,336,442 B2
Memory device with bottom electrode
Hsia-Wei Chen, Taipei (TW); Chih-Hung Pan, Taichung (TW); Chih-Hsiang Chang, Taichung (TW); Yu-Wen Liao, New Taipei (TW); and Wen-Ting Chu, Kaohsiung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jun. 12, 2023, as Appl. No. 18/333,145.
Application 18/333,145 is a division of application No. 16/912,341, filed on Jun. 25, 2020, granted, now 11,723,294.
Prior Publication US 2023/0329128 A1, Oct. 12, 2023
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/8416 (2023.02) [H10N 70/023 (2023.02); H10B 63/30 (2023.02); H10B 63/80 (2023.02); H10N 70/063 (2023.02); H10N 70/24 (2023.02); H10N 70/826 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a bottom electrode comprising a via portion in a dielectric layer, and a top portion over the dielectric layer, the top portion of the bottom electrode comprising a non-noble metal layer above the dielectric layer, and a noble metal layer above the non-noble metal layer;
a buffer element over the bottom electrode;
a metal-containing oxide portion over the buffer element, wherein the metal-containing oxide portion has a same metal material as that of the buffer element;
a resistance switch element over the metal-containing oxide portion; and
a top electrode over the resistance switch element.