US 12,336,441 B2
Resistive memory device and preparation method thereof
Wei Chang, Hefei (CN); Jiefang Deng, Hefei (CN); and Xiaoguang Wang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jun. 15, 2022, as Appl. No. 17/807,030.
Application 17/807,030 is a continuation of application No. PCT/CN2022/076303, filed on Feb. 15, 2022.
Claims priority of application No. 202110779767.9 (CN), filed on Jul. 9, 2021.
Prior Publication US 2023/0008157 A1, Jan. 12, 2023
Int. Cl. H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/253 (2023.02) [H10B 63/80 (2023.02); H10N 70/066 (2023.02); H10N 70/24 (2023.02); H10N 70/8833 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A preparation method of a resistive memory device, comprising:
providing a base, wherein a shallow trench isolation structure is formed in the base, and the shallow trench isolation structure isolates active regions arranged in an array in the base;
forming bit line trenches and gate trenches in the base, each of the gate trenches and one of the bit line trenches cross a same active region, and the active region is divided into a source region located between the gate trench and the shallow trench isolation structure, and a drain region located between the gate trench and the bit line trench;
forming a resistive material layer on a sidewall and a bottom of each of the bit line trenches; and
forming a bit line structure in each of the bit line trenches and a gate structure in each of the gate trenches through filling, wherein a variable resistor structure comprises the bit line structure and the resistive material layer;
forming a source lead structure on the source region;
forming a source metal wire layer on the base, wherein the source metal wire layer is in contact with the source lead structure.