| CPC H10N 60/128 (2023.02) [G06N 10/40 (2022.01); G06N 10/60 (2022.01); G11C 11/44 (2013.01); H10N 60/11 (2023.02)] | 15 Claims |

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1. An apparatus, comprising:
a semiconductor substrate having a quantum-well structure corresponding to one or more memory cells, each of the memory cells having a pattern of controllable electrodes, the electrodes laterally defining a physical sequence of two or more lateral regions of the quantum-well structure joined by one or more channels; and
one or more metal surface gates on the surface of the substrate substantially covering the two or more lateral regions, the one or more metal surface gates having a thickness that enables a substantial portion of light impinging thereupon to penetrate therethrough to the surface of the substrate; and
wherein the electrodes are controllable to deplete lateral areas of the quantum-well structure of charge carriers such that a 2-dimensional droplet of the charge carriers in the quantum-well structure is localized laterally along the substrate beneath the one or more metal surface gates;
wherein the one or more metal surface gates have one or more openings, each of the one or more openings having therein a respective dot-like electrode of the pattern of controllable electrodes; and
wherein each of the one or more dot-like electrodes is not in direct electrical contact with any of the one or more metal surface gates; and
wherein each of the one or more dot-like electrodes is in direct electrical contact with a corresponding electrical overpass bridge.
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