| CPC H10N 50/80 (2023.02) [H10B 61/00 (2023.02); H10N 50/01 (2023.02)] | 17 Claims |
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1. A semiconductor device comprising:
a substrate including a first region and a second region;
a contact insulating layer on the first region of the substrate and extending onto the second region of the substrate;
lower contact plugs penetrating the contact insulating layer on the first region of the substrate and spaced apart from each other in a first direction parallel to a top surface of the substrate;
data storage patterns respectively on the lower contact plugs and spaced apart from each other in the first direction;
lower conductive contacts penetrating the contact insulating layer on the second region of the substrate and spaced apart from each other in the first direction;
lower conductive lines respectively on the lower conductive contacts and spaced apart from each other in the first direction;
a first lower insulating layer on the contact insulating layer, on the first region of the substrate and interposed between the data storage patterns;
a second lower insulating layer on the contact insulating layer, on the second region of the substrate and interposed between the lower conductive lines;
a cell line structure on the data storage patterns and the first lower insulating layer, on the first region of the substrate, extending in the first direction, and electrically connected to the data storage patterns; and
an upper connection structure on the lower conductive lines and the second lower insulating layer, on the second region of the substrate, and electrically connected to the lower conductive lines,
wherein at least portions of the lower conductive lines are located at a same height as the data storage patterns, relative to the substrate,
wherein the upper connection structure comprises an upper conductive line that extends in the first direction, and upper conductive contacts that are arranged along a bottom surface of the upper conductive line and are spaced apart from each other in the first direction,
wherein the upper conductive contacts are connected to the lower conductive lines respectively, wherein the bottom surface of the upper conductive line is located at a height higher than a bottom surface of the cell line structure, relative to the substrate,
wherein a side surface of the cell line structure has a straight line shape continuously extending between the bottom surface of the cell line structure and a top surface of the cell line structure, when viewed in a sectional view, and
wherein the upper connection structure further comprises an upper barrier pattern and the upper conductive contacts are spaced apart from the lower conductive lines by the upper barrier pattern, and
wherein the upper conductive contacts and the upper barrier pattern at least partially extend into the lower conductive lines.
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