US 12,336,413 B2
Display panel, display device, and manufacturing method of display panel
Ping Wen, Beijing (CN); Shun Zhang, Beijing (CN); Yuanqi Zhang, Beijing (CN); Chang Luo, Beijing (CN); Wei Wang, Beijing (CN); Yu Wang, Beijing (CN); Tingliang Liu, Beijing (CN); Yang Zeng, Beijing (CN); and Yi Zhang, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/786,391
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Sep. 1, 2021, PCT No. PCT/CN2021/115874
§ 371(c)(1), (2) Date Jun. 16, 2022,
PCT Pub. No. WO2022/088942, PCT Pub. Date May 5, 2022.
Claims priority of application No. 202011194836.1 (CN), filed on Oct. 30, 2020.
Prior Publication US 2023/0012152 A1, Jan. 12, 2023
Int. Cl. H10K 59/40 (2023.01); G06F 3/041 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01); H10K 59/131 (2023.01); H10K 59/179 (2023.01); H10K 59/82 (2023.01); H10K 71/00 (2023.01); H10K 59/12 (2023.01)
CPC H10K 59/40 (2023.02) [G06F 3/0412 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 25/18 (2013.01); H10K 59/131 (2023.02); H10K 59/179 (2023.02); H10K 59/82 (2023.02); H10K 71/00 (2023.02); H01L 2224/039 (2013.01); H01L 2224/05018 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05558 (2013.01); H01L 2224/05562 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/29028 (2013.01); H01L 2224/32145 (2013.01); H10K 59/1201 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a display substrate having a display area and a non-display area surrounding the display area, wherein the display substrate comprises a substrate and an integrated circuit bonding portion arranged on one side of the substrate and located in the non-display area, and wherein the integrated circuit bonding portion comprises:
a pin;
a first passivation layer located on one side of the substrate adjacent to the pin, covering a peripheral area of the pin, and exposing a central area of the pin;
a first barrier layer located on one side of the first passivation layer away from the substrate and covering the first passivation layer and an edge of the first passivation layer connected to the pin;
a first metal layer located on one side of the first barrier layer away from the substrate, at least covering a central portion of the pin, and electrically connected to the pin; and
a touch control structure at least located in the display area of the display substrate;
wherein the display substrate further comprises:
a plurality of light-emitting elements arranged on one side of the substrate adjacent to the integrated circuit bonding portion and located in the display area; and
an encapsulation layer located between the plurality of light-emitting elements and the touch control structure, and configured to encapsulate the display substrate.