CPC H10K 59/131 (2023.02) [H10K 77/00 (2023.02); H10K 59/8051 (2023.02)] | 20 Claims |
1. An array substrate, comprising:
a plurality of pixel units arranged in an array, the pixel units comprising a plurality of sub-pixels;
a plurality of initialization signal lines arranged in a first conductive layer on the array substrate, extending along a first direction and arranged at intervals along a second direction, and configured to provide initialization signals to each of the sub-pixels, wherein the first direction and the second direction intersect;
a plurality of connection lines arranged in a second conductive layer on the array substrate, and extending along the second direction and arranged at intervals along the first direction, wherein:
the first conductive layer and the second conductive layer are an identical layer or different layers; and
projections of at least one of the initialization signal lines and at least one of the connection lines on the array substrate intersect and are electrically connected, such that the projections of the initialization signal lines and the connection lines on the array substrate form a grid structure,
wherein the array substrate comprises a base substrate and a first source-drain layer, a second source-drain layer, and an anode layer sequentially stacked on the base substrate.
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