US 12,336,318 B2
Image sensor and electronic apparatus including the same
Ji-Won Lee, Daegu (KR); Jeong-Jin Cho, Suwon-si (KR); Moo-Sup Lim, Yongin-si (KR); Sung-Young Seo, Bucheon-si (KR); and Hae-Won Lee, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 26, 2022, as Appl. No. 17/825,059.
Application 17/825,059 is a continuation of application No. 17/154,421, filed on Jan. 21, 2021.
Application 17/154,421 is a continuation of application No. 16/797,193, filed on Feb. 21, 2020, granted, now 11,302,737, issued on Apr. 12, 2022.
Application 16/797,193 is a continuation of application No. 15/854,356, filed on Dec. 26, 2017, granted, now 10,608,037, issued on Mar. 31, 2020.
Claims priority of application No. 10-2016-0180138 (KR), filed on Dec. 27, 2016.
Prior Publication US 2022/0285418 A1, Sep. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10F 39/00 (2025.01); H04N 25/77 (2023.01); H10F 39/18 (2025.01)
CPC H10F 39/813 (2025.01) [H04N 25/77 (2023.01); H10F 39/18 (2025.01); H10F 39/802 (2025.01); H10F 39/8037 (2025.01); H10F 39/811 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An image sensor, comprising:
a substrate;
a first shared pixel disposed in the substrate and including at least two photodiodes that share a first floating diffusion (FD) area;
a second shared pixel disposed in the substrate adjacent to the first shared pixel in a first direction and including at least two photodiodes that share a second FD area;
a first transistor (TR) set configured to be shared by the first shared pixel and comprising a first reset TR, a first source follower TR, and a first selection TR, which are arranged collinearly along the first direction:
a second TR set configured to be shared by the second shared pixel and comprising a second selection TR, a second source follower TR, and a second reset TR, which are arranged collinearly along the first direction;
a stack structure comprising a doped semiconductor layer and an insulating layer on the doped semiconductor layer, the stack structure disposed outside the first TR set and the second TR set in a plane parallel to an upper surface of the substrate and being positioned at the edge of each of the first TR set and the second TR set; and
a common vertical contact directly connected to a source region of the first selection TR and the second selection TR,
wherein the first TR set and the second TR set are in a mirror symmetry relationship with respect to the common vertical contact, and
wherein the stack structure comprises an isolation area positioned at the edge of each of the first TR set and the second TR set in the first direction, the first reset TR, an equivalent FD area and the isolation area positioned at the edge of the first TR set are arranged in order, and the insulating layer separates the equivalent FD area from the first FD area.