US 12,336,296 B2
Semiconductor device including source/drain contact having height below gate stack
Charles Chew-Yuen Young, Cupertino, CA (US); Chih-Liang Chen, Hsinchu (TW); Chih-Ming Lai, Hsinchu (TW); Jiann-Tyng Tzeng, Hsinchu (TW); Shun-Li Chen, Tainan (TW); Kam-Tou Sio, Hsinchu County (TW); Shih-Wei Peng, Hsinchu (TW); Chun-Kuang Chen, Hsinchu County (TW); and Ru-Gun Liu, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Dec. 1, 2023, as Appl. No. 18/526,395.
Application 18/167,651 is a division of application No. 17/092,100, filed on Nov. 6, 2020, granted, now 11,581,300, issued on Feb. 14, 2023.
Application 18/526,395 is a continuation of application No. 18/167,651, filed on Feb. 10, 2023, granted, now 11,862,623.
Application 17/092,100 is a continuation of application No. 16/216,843, filed on Dec. 11, 2018, granted, now 10,833,061, issued on Nov. 10, 2020.
Application 16/216,843 is a continuation of application No. 15/159,692, filed on May 19, 2016, granted, now 10,177,133, issued on Jan. 8, 2019.
Application 15/159,692 is a continuation in part of application No. 14/280,196, filed on May 16, 2014, granted, now 9,478,636, issued on Oct. 25, 2016.
Prior Publication US 2024/0096867 A1, Mar. 21, 2024
Int. Cl. H10D 89/10 (2025.01); G06F 30/394 (2020.01); H01L 21/768 (2006.01); H01L 23/485 (2006.01); H01L 23/528 (2006.01); H10D 30/01 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 86/01 (2025.01)
CPC H10D 89/10 (2025.01) [G06F 30/394 (2020.01); H01L 21/76895 (2013.01); H01L 23/485 (2013.01); H10D 84/013 (2025.01); H10D 84/0133 (2025.01); H10D 84/0135 (2025.01); H10D 84/0149 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H01L 21/76897 (2013.01); H01L 23/528 (2013.01); H01L 2924/0002 (2013.01); H10D 30/0227 (2025.01); H10D 64/021 (2025.01); H10D 86/011 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region;
a first separation spacer disposed on the first gate structure; and
a plurality of first vias on the first gate structure, wherein the plurality of first vias, that are arranged on opposite sides of the first separation spacer, are isolated from each other and apart from the first separation spacer by different distances.