US 12,336,294 B2
Gate-cut and separation techniques for enabling independent gate control of stacked transistors
Ruilong Xie, Niskayuna, NY (US); Nicolas Loubet, Guilderland, NY (US); Julien Frougier, Albany, NY (US); Lawrence A. Clevenger, Saratoga Springs, NY (US); Prasad Bhosale, Albany, NY (US); Junli Wang, Slingerlands, NY (US); Balasubramanian Pranatharthiharan, Santa Clara, CA (US); and Dechao Guo, Niskayuna, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Nov. 10, 2021, as Appl. No. 17/522,974.
Prior Publication US 2023/0142226 A1, May 11, 2023
Int. Cl. H10D 88/00 (2025.01); H10D 30/67 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 88/00 (2025.01) [H10D 30/6735 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10D 88/01 (2025.01)] 6 Claims
OG exemplary drawing
 
1. A device comprising:
vertically stacked transistors comprising at least one first transistor and at least one second transistor separated by a dielectric isolation layer; and
gate material adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material, the gate material being positioned on an underlayer;
wherein one end of the dielectric isolation layer is adjacent to the at least one second height vertical layer and another end is adjacent to another vertical layer, the another vertical layer comprising a top surface and a bottom surface;
wherein the top surface of the another vertical layer abuts a conductive portion of the gate material and the bottom surface abuts the underlayer.