US 12,336,291 B2
Semiconductor device
Takahiko Ishizu, Kanagawa (JP); and Seiichi Yoneda, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Mar. 8, 2024, as Appl. No. 18/599,439.
Application 18/599,439 is a continuation of application No. 17/047,740, granted, now 11,935,899, previously published as PCT/IB2019/052859, filed on Apr. 8, 2019.
Claims priority of application No. 2018-081075 (JP), filed on Apr. 20, 2018; and application No. 2018-085916 (JP), filed on Apr. 27, 2018.
Prior Publication US 2024/0355833 A1, Oct. 24, 2024
Int. Cl. H03K 19/00 (2006.01); H03K 19/003 (2006.01); H03K 19/017 (2006.01); H03K 19/094 (2006.01); H03K 19/20 (2006.01); H10D 62/80 (2025.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)
CPC H10D 86/60 (2025.01) [H03K 19/00315 (2013.01); H03K 19/017 (2013.01); H03K 19/0941 (2013.01); H03K 19/20 (2013.01); H10D 62/80 (2025.01); H10D 86/021 (2025.01); H10D 86/441 (2025.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first input terminal and a second input terminal;
a first output terminal and a second output terminal;
a first wiring to a third wiring; and
first to eighth transistors,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring, one of a gate and a back gate is electrically connected to the first input terminal, and the other of the source and the drain and the other of the gate and the back gate are electrically connected to a gate and a back gate of the second transistor,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring and the other of the source and the drain is electrically connected to the second output terminal,
wherein one of a source and a drain of the third transistor is electrically connected to the first wiring, one of a gate and a back gate is electrically connected to the second input terminal, and the other of the source and the drain and the other of the gate and the back gate are electrically connected to a gate and a back gate of the fourth transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the second wiring and the other of the source and the drain is electrically connected to the first output terminal,
wherein a gate and a back gate of the fifth transistor are electrically connected to the first input terminal, one of a source and a drain is electrically connected to the gate and the back gate of the fourth transistor, and the other of the source and the drain is electrically connected to the third wiring,
wherein a gate and a back gate of the sixth transistor are electrically connected to the first input terminal, one of a source and a drain is electrically connected to the first output terminal, and the other of the source and the drain is electrically connected to the third wiring,
wherein a gate and a back gate of the seventh transistor are electrically connected to the second input terminal, one of a source and a drain is electrically connected to the gate and the back gate of the second transistor, and the other of the source and the drain is electrically connected to the third wiring, and
wherein a gate and a back gate of the eighth transistor are electrically connected to the second input terminal, one of a source and a drain is electrically connected to the second output terminal, and the other of the source and the drain is electrically connected to the third wiring.