| CPC H10D 86/60 (2025.01) [G09G 3/3225 (2013.01); H10D 86/0221 (2025.01); H10D 86/481 (2025.01); G09G 2300/0426 (2013.01); G09G 2300/043 (2013.01); G09G 2300/0452 (2013.01); G09G 2300/0842 (2013.01); G09G 2320/0233 (2013.01); G09G 2330/02 (2013.01); H10D 86/0251 (2025.01); H10K 59/122 (2023.02)] | 16 Claims |
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1. A display substrate, comprising a base substrate and a plurality of subpixels arranged in an array form on the base substrate, wherein the plurality of subpixels is arranged in rows, and each row of subpixels comprises N subpixels arranged in sequence along a first direction, where N is a positive integer;
each subpixel comprises a subpixel driving circuitry, the subpixel driving circuitry comprises a driving transistor and a first transistor, a first electrode of the first transistor is coupled to a second electrode of the driving transistor, a second electrode of the first transistor is coupled to a gate electrode of the driving transistor, and an active layer of the first transistor comprises a first semiconductor portion and a second semiconductor portion spaced apart from each other, and a conductor portion coupled to the first semiconductor portion and the second semiconductor portion;
wherein each subpixel further comprises a power source signal line, at least a part of the power source signal line extends in a second direction, and a voltage stabilizing electrode is coupled to the power source signal line; and
the voltage stabilizing electrode comprises a first portion and a second portion coupled to each other, an orthogonal projection of the first portion onto the base substrate overlaps an orthogonal projection of the power source signal line onto the base substrate at an overlapping region where the first portion is coupled to the power source signal line, at least a part of the second portion extends along the first direction to a next subpixel in the first direction, and an orthogonal projection of the conductor portion onto the base substrate overlaps an orthogonal projection of a second portion of a voltage stabilizing electrode of a previous subpixel of the subpixel to which the conductor portion belongs in the first direction onto the substrate; and the voltage stabilizing electrode is L-shaped,
wherein each subpixel further comprises a data line, and at least a part of the data line extends in a second direction intersecting the first direction,
wherein the subpixel driving circuitry further comprises a data write-in transistor, a gate electrode of which is coupled to the gate line, a first electrode of which is coupled to the data line, and a second electrode of which is coupled to the first electrode of the driving transistor,
wherein the orthogonal projection of the second portion onto the base substrate overlaps an orthogonal projection of the first electrode of the data write-in transistor onto the base substrate, and the orthogonal projection of the second portion onto the base substrate overlaps an orthogonal projection of the data line onto the base substrate, and the orthogonal projection of the second portion onto the base substrate is between an orthogonal projection of the first transistor onto the base substrate and an orthogonal projection of a coupling position of the first electrode of the data write-in transistor and the data line,
the plurality of subpixels arranged in rows comprises red subpixels, blue subpixels and green subpixels, and are arranged in a diamond shape, in each row, a red subpixel, a green subpixel, a blue subpixel, and a green subpixel are arranged sequentially, in the first direction, subpixels at a first column are the red subpixels or the blue subpixels, subpixels at last column are the green subpixels, the first boundary is a boundary where the green subpixels are located, the voltage stabilizing electrodes stabilize subpixel driving circuitries of other subpixels except red subpixels or blue subpixels in the first column;
wherein a second portion of a voltage stabilizing electrode in the last column only occludes a first electrode of a data write-in transistor of a subpixel driving circuitry in the last column, and a second portion of a voltage stabilizing electrode in remaining columns obscures a first electrode of a data write-in transistor of a subpixel driving circuitry in its own column and a conductor portion of a first transistor of a subpixel driving circuitry in its next column;
the first electrode of the data write-in transistor is integrated in the active layer of the first transistor.
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