| CPC H10D 86/60 (2025.01) [H10D 86/01 (2025.01); H10D 86/0221 (2025.01); H10D 86/201 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/481 (2025.01); H10D 86/80 (2025.01)] | 19 Claims |
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1. A method used in forming an array of vertical transistors, comprising:
forming laterally-spaced and horizontally-elongated line constructions in a column direction; the line constructions comprising insulator material, metal material above the insulator material, transistor material above the metal material, and insulating material on lateral sides of the insulator material, the metal material, and the transistor material; the transistor material comprising an upper source/drain region above a channel region of what will be individual vertical transistors, the insulator material of the line constructions being above conductive material;
forming a horizontally-elongated conductive line in the column direction between immediately-laterally-adjacent of the line constructions and directly against the conductive material, the conductive lines individually comprising a top surface that is higher than a top surface of the metal material and at or below a bottom of the channel region;
after forming the conductive lines, etching the transistor material to form spaced pillars individually comprising the upper source/drain region and the channel region of the individual vertical transistors; and
forming a horizontally-elongated conductive gate line operatively aside the channel region of individual of the pillars that interconnects a respective plurality of the vertical transistors in a row direction.
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