US 12,336,283 B1
Three-dimensional stacked semiconductor device including simplified source/drain contact area
Keumseok Park, Slingerlands, NY (US); Edward Namkyu Cho, Albany, NY (US); and Kang-ill Seo, Springfield, VA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 14, 2024, as Appl. No. 18/947,649.
Claims priority of provisional application 63/644,209, filed on May 8, 2024.
Int. Cl. H10D 84/85 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 88/00 (2025.01)
CPC H10D 84/856 (2025.01) [H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 84/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01); H10D 88/01 (2025.01)] 20 Claims
OG exemplary drawing
 
13. A semiconductor device comprising:
a 1st source/drain pattern for a 1st transistor;
a 2nd source/drain pattern for a 2nd transistor, above the 1st source/drain pattern, the 2nd source/drain pattern having a smaller width than the 1st source/drain pattern in a channel-width direction;
a 1st isolation layer surrounding the 1st source/drain pattern;
a 2nd isolation layer surrounding the 2nd source/drain pattern, the 1st and 2nd isolation layers comprising a first material;
a liner surrounding the 1st source/drain pattern, the liner comprising a 2nd material; and
a contact structure on the 1st source/drain pattern,
wherein the contact structure penetrates the 2nd isolation layer and the liner to contact the 1st source/drain pattern without penetrating the 1st isolation layer.