US 12,336,282 B2
Semiconductor device having different source/drain junction depths and fabrication method thereof
Ta-Chun Lin, Hsinchu (TW); Chun-Jun Lin, Hsinchu (TW); Kuo-Hua Pan, Hsinchu (TW); and Jhon-Jhy Liaw, Zhudong Township, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 29, 2022, as Appl. No. 17/852,642.
Prior Publication US 2024/0006414 A1, Jan. 4, 2024
Int. Cl. H10D 84/85 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/856 (2025.01) [H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01); H10D 84/017 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor device, comprising:
forming a first fin in a first transistor region of a semiconductor substrate and a second fin in a second transistor region of the semiconductor substrate;
forming a first dummy gate structure across the first fin and a second dummy gate structure across the second fin;
selectively introducing atomic or ionic species into the second fin on opposite sides of the second dummy gate structure after forming the first and second dummy gate structures;
etching portions of the first fin and portions of the second fin after selectively introducing the atomic or ionic species, so as to form first recesses with a first depth in the first fin on opposite sides of the first dummy gate structure and second recesses with a second depth in the second fin on opposite sides of the second dummy gate structure, wherein the second depth is different than the first depth; and
forming first source/drain features in the first recesses and second source/drain features in the second recesses.