US 12,336,281 B2
Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof
Chia-Hao Pao, Kaohsiung (TW); Chih-Hsuan Chen, Hsinchu (TW); Lien-Jung Hung, Taipei (TW); and Shih-Hao Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Feb. 19, 2024, as Appl. No. 18/581,241.
Application 17/739,758 is a division of application No. 16/678,695, filed on Nov. 8, 2019, granted, now 11,329,042, issued on May 10, 2022.
Application 18/581,241 is a continuation of application No. 17/739,758, filed on May 9, 2022, granted, now 11,908,866.
Claims priority of provisional application 62/773,549, filed on Nov. 30, 2018.
Prior Publication US 2024/0234421 A1, Jul. 11, 2024
Int. Cl. H10D 84/85 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/853 (2025.01) [H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 64/017 (2025.01); H10D 64/513 (2025.01); H10D 64/519 (2025.01); H10D 84/0177 (2025.01); H10D 84/0179 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device structure comprising:
a gate dielectric layer that extends along a first direction and spans a first device region, a boundary region directly adjacent to the first device region, and a second device region directly adjacent to the boundary region, wherein the gate dielectric layer is disposed on a first semiconductor layer in the first device region, a second semiconductor layer in the second device region, and an isolation structure in the boundary region;
a p-type work function layer disposed on the gate dielectric layer, wherein the p-type work function layer extends along the first direction and spans the first device region, the boundary region, and the second device region and further wherein:
the p-type work function layer has a first thickness in the first device region, a second thickness in the boundary region, and a third thickness in the second device region, wherein the first thickness, the second thickness, and the third thickness are along a second direction different than the first direction, and
the first thickness is less than the second thickness, the first thickness is less than the third thickness, and the second thickness is greater than the third thickness; and
a first n-type work function layer and a second n-type work function layer disposed on the p-type work function layer, wherein the first n-type work function layer extends along the first direction and spans the first device region, the second n-type work function layer extends along the first direction and spans the second device region, and the p-type work function layer separates the first n-type work function layer and the second n-type work function layer.