US 12,336,276 B2
Semiconductor device and fabrication method thereof
Shin-Cheng Lin, Hsinchu County (TW); and Chia-Ching Huang, Taoyuan (TW)
Assigned to Vanguard International Semiconductor Corporation, Hsinchu (TW)
Filed by Vanguard International Semiconductor Corporation, Hsinchu (TW)
Filed on Jan. 16, 2023, as Appl. No. 18/097,291.
Prior Publication US 2024/0243121 A1, Jul. 18, 2024
Int. Cl. H10D 84/80 (2025.01); H10D 84/01 (2025.01); H10D 84/05 (2025.01)
CPC H10D 84/811 (2025.01) [H10D 84/05 (2025.01); H10D 84/01 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate, including an active element region and a passive element region;
a compound semiconductor channel layer, a compound semiconductor barrier layer, and a first compound semiconductor cap layer, disposed in sequence on the substrate and located in the active element region;
a gate electrode, disposed on the first compound semiconductor cap layer;
a source electrode and a drain electrode, disposed on the compound semiconductor barrier layer, respectively located on two sides of the gate electrode to construct a high electron mobility transistor; and
a second compound semiconductor cap layer, disposed on the substrate and located in the passive element region to construct a resistor.