US 12,336,271 B2
Semiconductor devices and methods of manufacturing thereof
Shih-Yao Lin, New Taipei (TW); Chen-Ping Chen, Toucheng Township (TW); Chen-Yui Yang, Hsinchu (TW); Hsiao Wen Lee, Hsinchu (TW); and Ming-Ching Chang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 28, 2021, as Appl. No. 17/460,203.
Prior Publication US 2023/0067425 A1, Mar. 2, 2023
Int. Cl. H10D 62/80 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H01L 21/3213 (2006.01)
CPC H10D 84/038 (2025.01) [H10D 84/0135 (2025.01); H10D 84/0149 (2025.01); H10D 84/0151 (2025.01); H10D 84/83 (2025.01); H01L 21/32134 (2013.01); H01L 21/32137 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first stack structure comprising a first plurality of channel layers vertically spaced from one another, wherein the first plurality of channel layers extend along a first direction;
a second stack structure comprising a second plurality of channel layers vertically spaced from one another, wherein the second plurality of channel layers also extend along the first direction;
a first dielectric fin structure that also extends along the first direction;
a first gate structure that extends along a second direction perpendicular to the first direction, wherein the first gate structure comprises a first portion that wraps around each of the first plurality of channel layers and a second portion that wraps around each of the second plurality of channel layers, and wherein the first dielectric fin structure separates the first and second portions from each other along the second direction;
wherein the first gate structure further comprises a third portion that connects the first and second portions to each other and is vertically disposed below the first dielectric fin structure.