US 12,336,269 B2
Semiconductor device and manufacturing method thereof
Peng-Soon Lim, Johor (MY); and Zi-Wei Fang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jan. 18, 2024, as Appl. No. 18/416,737.
Application 16/914,287 is a division of application No. 16/103,724, filed on Aug. 14, 2018, granted, now 10,707,131, issued on Jul. 7, 2020.
Application 18/416,737 is a continuation of application No. 17/826,129, filed on May 26, 2022, granted, now 11,915,981.
Application 17/826,129 is a continuation of application No. 16/914,287, filed on Jun. 27, 2020, granted, now 11,348,837, issued on May 31, 2022.
Prior Publication US 2024/0234212 A1, Jul. 11, 2024
Int. Cl. H10D 84/01 (2025.01); H01L 21/285 (2006.01); H10D 64/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)
CPC H10D 84/014 (2025.01) [H10D 84/0142 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01); H01L 21/28562 (2013.01); H01L 21/28568 (2013.01); H10D 64/017 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a first gate structure over the substrate and comprising:
a first gate dielectric; and
a first work function metal layer over the first gate dielectric;
first gate spacers on opposite sidewalls of the first gate structure;
a first tungsten layer spanning over the first gate structure, wherein a top surface of the first tungsten layer is lower than top surfaces of the first gate spacers;
a hard mask over the first tungsten layer; and
a liner lining the hard mask, wherein sidewalls and a bottom surface of the hard mask are covered by the liner.