US 12,336,268 B2
Gallium nitride (GaN) integrated circuit technology
Nicole K. Thomas, Portland, OR (US); Samuel Bader, Hillsboro, OR (US); Marko Radosavljevic, Portland, OR (US); Han Wui Then, Portland, OR (US); Pratik Koirala, Portland, OR (US); and Nityan Nair, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 13, 2021, as Appl. No. 17/402,054.
Prior Publication US 2023/0047449 A1, Feb. 16, 2023
Int. Cl. H01L 27/06 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/775 (2006.01); H01L 29/778 (2006.01); H01L 29/786 (2006.01); H10D 30/43 (2025.01); H10D 30/47 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/85 (2025.01); H10D 64/00 (2025.01); H10D 84/01 (2025.01)
CPC H10D 84/01 (2025.01) [H01L 21/02381 (2013.01); H01L 21/0243 (2013.01); H01L 21/0254 (2013.01); H10D 30/43 (2025.01); H10D 30/475 (2025.01); H10D 30/6735 (2025.01); H10D 30/6743 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/8503 (2025.01); H10D 64/111 (2025.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a substrate comprising silicon, the substrate having a top surface;
a first trench in the substrate, the first trench having a first width;
a second trench in the substrate, the second trench having a second width less than the first width;
a first island in the first trench, the first island comprising gallium and nitrogen and having first corner facets below the top surface of the substrate;
a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets below the top surface of the substrate; and
a hardmask material adjacent to the first corner facets and the second corner facets.