US 12,336,266 B2
Methods of forming gate structures with uniform gate length
Shahaji B. More, Hsinchu (TW); Cheng-Han Lee, New Taipei (TW); and Shih-Chieh Chang, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 9, 2021, as Appl. No. 17/226,905.
Claims priority of provisional application 63/112,758, filed on Nov. 12, 2020.
Prior Publication US 2022/0149176 A1, May 12, 2022
Int. Cl. H10D 64/66 (2025.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/00 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/85 (2025.01)
CPC H10D 64/671 (2025.01) [H01L 21/02603 (2013.01); H01L 21/30604 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/021 (2025.01); H10D 62/121 (2025.01); H10D 64/018 (2025.01); H10D 84/85 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A method comprising:
depositing a first semiconductor layer over a substrate;
depositing a second semiconductor layer over the first semiconductor layer;
depositing a third semiconductor layer over the second semiconductor layer, wherein a germanium concentration of the first semiconductor layer is greater than that of the third semiconductor layer;
doping the first semiconductor layer with boron, wherein a first boron concentration of the first semiconductor layer is non-uniform, wherein the first boron concentration varies along a thickness direction of the first semiconductor layer, wherein the first boron concentration decreases continuously from a first location of the first semiconductor layer to a second location of the first semiconductor layer, remains constant from the second location of the first semiconductor layer to a third location of the first semiconductor layer, and increases continuously from the third location of the first semiconductor layer to a fourth location of the first semiconductor layer, wherein the first location, the second location, the third location, and the fourth location of the first semiconductor layer are aligned along a same line that extends along the thickness direction of the first semiconductor layer;
doping the third semiconductor layer with boron;
etching a first opening through the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer;
recessing the first semiconductor layer and the third semiconductor layer through the first opening, wherein after recessing the first semiconductor layer and the third semiconductor layer, the first semiconductor layer has a same width as the third semiconductor layer;
forming a source/drain region in the first opening; and
replacing the first semiconductor layer and the third semiconductor layer with a gate structure, wherein the gate structure is disposed around the second semiconductor layer.