US 12,336,263 B2
Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
Walter A. Harrison, Palo Alto, CA (US); Paul A. Clifton, Palo Alto, CA (US); Andreas Goebel, Palo Alto, CA (US); and R. Stockton Gaines, Santa Monica, CA (US)
Assigned to Acorn Semi, LLC, Palo Alto, CA (US)
Filed by Acorn Semi, LLC, Palo Alto, CA (US)
Filed on Sep. 26, 2023, as Appl. No. 18/474,948.
Application 18/474,948 is a continuation of application No. 18/173,541, filed on Feb. 23, 2023, granted, now 11,804,533.
Application 18/173,541 is a continuation of application No. 17/247,803, filed on Dec. 23, 2020, granted, now 11,610,974, issued on Mar. 21, 2023.
Application 17/247,803 is a continuation of application No. 16/706,510, filed on Dec. 6, 2019, granted, now 10,879,366, issued on Dec. 29, 2020.
Application 16/706,510 is a continuation of application No. 15/684,707, filed on Aug. 23, 2017, granted, now 10,505,005, issued on Dec. 10, 2019.
Application 15/684,707 is a continuation of application No. 15/146,562, filed on May 4, 2016, granted, now 9,755,038, issued on Sep. 5, 2017.
Application 15/146,562 is a continuation of application No. 14/360,473, granted, now 9,362,376, issued on Jun. 7, 2016, previously published as PCT/US2012/060893, filed on Oct. 18, 2012.
Claims priority of provisional application 61/563,478, filed on Nov. 23, 2011.
Prior Publication US 2024/0030306 A1, Jan. 25, 2024
Int. Cl. H10D 64/64 (2025.01); H01L 21/283 (2006.01); H01L 21/285 (2006.01); H01L 21/324 (2006.01); H10D 62/40 (2025.01); H10D 62/83 (2025.01); H10D 62/832 (2025.01); H10D 64/62 (2025.01)
CPC H10D 64/64 (2025.01) [H01L 21/283 (2013.01); H01L 21/28512 (2013.01); H01L 21/28518 (2013.01); H01L 21/324 (2013.01); H10D 62/405 (2025.01); H10D 62/83 (2025.01); H10D 62/832 (2025.01); H10D 64/62 (2025.01)] 14 Claims
OG exemplary drawing
 
1. An electrical device, comprising:
an n-channel transistor including a first electrical contact, comprising:
a first semiconductor region forming a first source/drain region of the n-channel transistor, the first source/drain region being an n-type doped region of the n-channel transistor;
a first ordered monolayer of atoms of a material in contact with a surface of the first semiconductor region, the atoms of the first ordered monolayer being coordinated with and bonded to atoms of the first semiconductor region at the surface of the first semiconductor region; and
a metallic material disposed over the first ordered monolayer of atoms such that the first ordered monolayer layer of atoms is interposed between the metallic material and the first semiconductor region enabling an electrical current to pass between the metallic material and the first semiconductor region through the first ordered monolayer of atoms when the first electrical contact is electrically biased; and
a p-channel transistor including a second electrical contact, comprising:
a second semiconductor region forming a second source/drain region of the p-channel transistor, the second source/drain region being a p-type doped region of the p-channel transistor;
the same metallic material disposed over the second semiconductor region, enabling an electrical current to pass between the metallic material and the second semiconductor region when the second electrical contact is electrically biased.