US 12,336,258 B2
Semiconductor structure
Yen-Ching Wu, Taoyuan (TW); Chung-Kai Lin, Taipei (TW); Kuan-Lun Cheng, Hsin-Chu (TW); Wen-Chien Lin, Taoyuan (TW); and Chih-Ling Hsiao, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 25, 2022, as Appl. No. 17/727,846.
Prior Publication US 2023/0343840 A1, Oct. 26, 2023
Int. Cl. H10D 64/23 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01)
CPC H10D 64/258 (2025.01) [H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 64/01 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
an insulator;
a semiconductor fin protruding from the insulator;
a gate stack disposed on the semiconductor fin and the insulator;
a gate contact disposed on and electrically connected to the gate stack;
a source/drain material disposed on the semiconductor fin; and
a source/drain contact structure disposed on and electrically connected to the source/drain material;
wherein the semiconductor fin extends along a first direction, the gate stack extends along a second direction different from the first direction, and an offset S in the second direction between the gate contact and the source/drain contact structure satisfied: 0<S≤(W/2+D/2), wherein W is a width of the semiconductor fin, and D is a dimension of the gate contact.