US 12,336,256 B2
Semiconductor structure with metal ion capture layer
Yi Ting Liao, Changhua (TW); Chao-Chi Chen, Tainan (TW); Bo-Wei Chen, Kaohsiung (TW); Shi Sheng Hu, Tainan (TW); and Shun Chi Tsai, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 14, 2022, as Appl. No. 17/720,481.
Prior Publication US 2023/0335603 A1, Oct. 19, 2023
Int. Cl. H10D 64/00 (2025.01); H01L 21/28 (2006.01); H10D 64/66 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 64/118 (2025.01) [H01L 21/28088 (2013.01); H10D 64/667 (2025.01); H10D 84/0177 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first fin structure and a second fin structure on a substrate;
forming a first gate structure over the first fin structure and a second gate structure over the second fin structure, wherein the first gate structure adjoins the second gate structure;
forming a dielectric layer on the first and second gate structures;
removing a portion of the dielectric layer above an adjoining portion of the first and second gate structures to form an opening; and
forming a metal ion capture layer in the opening.