| CPC H10D 64/111 (2025.01) [H10D 30/015 (2025.01); H10D 30/60 (2025.01); H10D 62/115 (2025.01); H10D 62/824 (2025.01); H10D 62/8503 (2025.01); H10D 64/112 (2025.01)] | 19 Claims |

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1. A semiconductor device comprising:
a semiconductor substrate that includes an upper surface and a channel;
a first dielectric layer disposed over the upper surface of the semiconductor substrate;
a first current-carrying electrode and a second current-carrying electrode formed over the semiconductor substrate within openings formed in the first dielectric layer, wherein the first current-carrying electrode and the second current-carrying electrode are electrically coupled to the channel;
a control electrode formed over the semiconductor substrate and disposed between the first current-carrying electrode and the second current-carrying electrode and over the first dielectric layer, wherein the control electrode is electrically coupled to the channel;
a first conductive element formed over the first dielectric layer, adjacent to the control electrode between the control electrode and the second current-carrying electrode;
a second dielectric layer disposed over the control electrode and over the first conductive element; and
a second conductive element disposed over the second dielectric layer and directly over the first conductive element and between the first conductive element and the control electrode; and
an opening formed in the second dielectric layer over the first conductive element, wherein the first conductive element is electrically coupled to the second conductive element through an electrical connection formed in the opening formed in the second dielectric layer.
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