US 12,336,251 B2
Formation of transistor gates
Yen-Jui Chiu, Hsinchu (TW); Yao-Teng Chuang, Hsinchu (TW); and Kuei-Lun Lin, Keelung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jan. 3, 2024, as Appl. No. 18/403,523.
Application 18/403,523 is a continuation of application No. 17/340,037, filed on Jun. 6, 2021, granted, now 11,901,436.
Claims priority of provisional application 63/157,499, filed on Mar. 5, 2021.
Prior Publication US 2024/0154024 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 64/01 (2025.01); H10D 30/67 (2025.01); H10D 86/01 (2025.01)
CPC H10D 64/017 (2025.01) [H10D 64/01 (2025.01); H10D 86/0221 (2025.01); H10D 86/0231 (2025.01); H10D 30/6735 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
depositing a first gate dielectric layer over a first semiconductor channel and a second semiconductor channel;
depositing a second gate dielectric layer over the first gate dielectric layer;
forming a layer over the second gate dielectric layer by using one or more atomic layer deposition (ALD) cycles each comprising sequentially performing a first pulse step for a first pulse time, a first purge step for a first purge time, a second pulse step for a second pulse time, and a second purge step for a second purge time, wherein a ratio of the first purge time to the first pulse time is greater than a ratio of the second purge time to the second pulse time;
patterning the layer to expose a portion of the second gate dielectric layer; and
etching the exposed portion of the second gate dielectric layer.