US 12,336,249 B2
Gate spacer and formation method thereof
Yi-Rui Chen, Yilan County (TW); Yi-Fan Chen, New Taipei (TW); Szu-Ying Chen, Hsinchu (TW); Sen-Hong Syue, Hsinchu County (TW); Huicheng Chang, Tainan (TW); and Yee-Chia Yeo, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Mar. 16, 2022, as Appl. No. 17/696,257.
Prior Publication US 2023/0299175 A1, Sep. 21, 2023
Int. Cl. H10D 64/01 (2025.01); H01L 21/02 (2006.01); H10D 64/66 (2025.01); H10D 30/01 (2025.01)
CPC H10D 64/017 (2025.01) [H01L 21/0214 (2013.01); H01L 21/02211 (2013.01); H01L 21/0228 (2013.01); H01L 21/02323 (2013.01); H01L 21/02337 (2013.01); H01L 21/02343 (2013.01); H10D 64/01 (2025.01); H10D 64/671 (2025.01); H10D 30/024 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, comprising:
forming a sacrificial gate structure over a substrate;
depositing a spacer layer on the sacrificial gate structure in a conformal manner;
performing a multi-step oxidation process to the spacer layer;
etching the spacer layer to form gate sidewall spacers on opposite sidewalls of the sacrificial gate structure;
removing the sacrificial gate structure to form a trench between the gate sidewalls spacers; and
forming a metal gate structure in the trench.