US 12,336,243 B2
Lateral bipolar transistor with gated collector
Alexander Derrickson, Saratoga Springs, NY (US); Vibhor Jain, Williston, VT (US); Judson R. Holt, Ballston Lake, NY (US); Jagar Singh, Clifton Park, NY (US); and Mankyu Yang, Fishkill, NY (US)
Assigned to GLOBALFOUNDRIES U.S. Inc., Malta, NY (US)
Filed by GLOBALFOUNDRIES U.S. Inc., Malta, NY (US)
Filed on Jan. 5, 2024, as Appl. No. 18/405,621.
Application 18/405,621 is a division of application No. 17/525,256, filed on Nov. 12, 2021, granted, now 11,935,923.
Claims priority of provisional application 63/236,425, filed on Aug. 24, 2021.
Prior Publication US 2024/0136400 A1, Apr. 25, 2024
Int. Cl. H10D 62/13 (2025.01); H10D 10/60 (2025.01); H10D 10/80 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01); H10D 64/23 (2025.01)
CPC H10D 62/137 (2025.01) [H10D 10/60 (2025.01); H10D 10/80 (2025.01); H10D 62/115 (2025.01); H10D 62/134 (2025.01); H10D 62/136 (2025.01); H10D 62/184 (2025.01); H10D 64/231 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region;
a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers;
an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers; and
a polysilicon spacer adjacent to the first spacer and electrically contacting to the collector region.