| CPC H10D 62/121 (2025.01) [H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01)] | 20 Claims |
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1. A method, comprising:
defining a first channel region of a first transistor by forming a first trench in a semiconductor layer over a semiconductor substrate;
forming a dielectric barrier on the semiconductor substrate in a bottom of the first trench; and
growing a first source/drain region of the first transistor over the dielectric barrier and in contact with the first channel region, wherein the dielectric barrier electrically isolates the first source region from the semiconductor substrate;
forming a second channel region of a second transistor by forming a second trench in the semiconductor layer over the semiconductor substrate;
selectively forming a masking layer over the first transistor; and
growing a second source/drain region of the second transistor in contact with the semiconductor substrate at a bottom of the second trench, wherein the first source/drain region and the second source/drain region have a same first conductivity type.
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