| CPC H10D 62/102 (2025.01) [H10D 12/481 (2025.01); H10D 30/665 (2025.01); H10D 30/668 (2025.01)] | 5 Claims |
|
1. A semiconductor device, comprising:
a first semiconductor layer of a first conductivity type, having a first main surface and a second main surface that are opposite to each other;
a second semiconductor layer of the first conductivity type, provided at the first main surface of the first semiconductor layer, the second semiconductor layer having an impurity concentration that is higher than an impurity concentration of the first semiconductor layer, the second semiconductor layer having a first surface and a second surface that are opposite to each other, the second surface thereof facing the first semiconductor layer;
a first semiconductor region of a second conductivity type, provided at the first surface of the second semiconductor layer;
a second semiconductor region of the first conductivity type, selectively provided in the first semiconductor region;
a trench that penetrates through the second semiconductor region and the first semiconductor region and reaches the first semiconductor layer;
a gate insulating film provided in the trench, along a bottom and sidewalls of the trench;
a gate electrode provided on the gate insulating film in the trench;
a third semiconductor region of the second conductivity type, selectively provided in the first semiconductor layer to surround the bottom of the trench;
a fourth semiconductor region provided at the second main surface of the first semiconductor layer;
a fifth semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer, the fifth semiconductor region having an impurity concentration that is lower than the impurity concentration of the second semiconductor layer;
a first electrode that is electrically connected to the first semiconductor region and the second semiconductor region; and
a second electrode that is electrically connected to the fourth semiconductor region, wherein
the fifth semiconductor region has
a first surface and a second surface that are opposite to each other, the first surface being in contact with the first semiconductor region, the second surface being in contact with the third semiconductor region, and
a side surface that is in contact with the gate insulating film.
|