US 12,336,230 B1
IC structure with MFMIS memory cell and CMOS transistor
Stefan Dünkel, Dresden (DE); Dominik Martin Kleimaier, Dresden (DE); Halid Mulaosmanovic, Dresden (DE); Johannes Müller, Dresden (DE); and Sven Beyer, Dresden (DE)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Aug. 13, 2024, as Appl. No. 18/802,233.
Int. Cl. H10D 30/69 (2025.01); H01L 21/762 (2006.01); H10B 51/30 (2023.01); H10B 51/40 (2023.01); H10D 64/66 (2025.01)
CPC H10D 30/701 (2025.01) [H01L 21/76224 (2013.01); H10B 51/30 (2023.02); H10B 51/40 (2023.02); H10D 64/661 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory cell on a semiconductor substrate; and
a complementary metal-oxide semiconductor (CMOS) transistor adjacent the MFMIS memory cell on the semiconductor substrate
a metal-ferroelectric-insulator-semiconductor (MFIS) memory cell adjacent at least one of the MFMIS memory cell and the CMOS transistor, the MFIS memory cell sharing the semiconductor substrate with the MFMIS memory cell and the CMOS transistor.