US 12,336,229 B2
Split gate memory device and method of fabricating the same
Chang-Ming Wu, New Taipei (TW); Wei Cheng Wu, Zhubei (TW); Shih-Chang Liu, Alian Township (TW); Harry-Hak-Lay Chuang, Zhubei (TW); and Chia-Shiung Tsai, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on May 17, 2023, as Appl. No. 18/318,867.
Application 16/166,603 is a division of application No. 15/332,115, filed on Oct. 24, 2016, granted, now 10,147,794, issued on Dec. 4, 2018.
Application 18/318,867 is a continuation of application No. 17/347,848, filed on Jun. 15, 2021, granted, now 11,658,224.
Application 17/347,848 is a continuation of application No. 16/705,508, filed on Dec. 6, 2019, granted, now 11,056,566, issued on Jul. 6, 2021.
Application 16/705,508 is a continuation of application No. 16/166,603, filed on Oct. 22, 2018, granted, now 10,516,026, issued on Dec. 24, 2019.
Application 15/332,115 is a continuation of application No. 14/182,952, filed on Feb. 18, 2014, granted, now 9,484,351, issued on Nov. 1, 2016.
Prior Publication US 2023/0290845 A1, Sep. 14, 2023
Int. Cl. H10D 30/69 (2025.01); H10B 41/30 (2023.01); H10B 41/35 (2023.01); H10B 43/30 (2023.01); H10B 43/35 (2023.01); H10D 30/01 (2025.01); H10D 30/68 (2025.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01)
CPC H10D 30/696 (2025.01) [H10B 41/30 (2023.02); H10B 41/35 (2023.02); H10B 43/30 (2023.02); H10B 43/35 (2023.02); H10D 30/0411 (2025.01); H10D 30/0413 (2025.01); H10D 30/6891 (2025.01); H10D 30/69 (2025.01); H10D 30/697 (2025.01); H10D 64/015 (2025.01); H10D 64/035 (2025.01); H10D 64/037 (2025.01); H10D 64/693 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a source/drain region arranged within a substrate;
a select gate arranged over the substrate;
a memory gate arranged over the substrate;
an inter-gate dielectric structure arranged between the memory gate and the select gate;
a conductive contact disposed on the source/drain region and vertically extending from a bottom of the select gate to a top of the select gate, the select gate being closer to the conductive contact than the memory gate, wherein the select gate has a first outermost sidewall that faces away from the memory gate and a second outermost sidewall that faces the memory gate, the first outermost sidewall being taller than the second outermost sidewall; and
wherein the first outermost sidewall is parallel with an outermost sidewall of the memory gate that faces the select gate.