US 12,336,226 B2
Semiconductor device structure including stacked nanostructures
Jung-Hung Chang, Changhua County (TW); Zhi-Chang Lin, Zhubei (TW); Shih-Cheng Chen, New Taipei (TW); Chien-Ning Yao, Hsinchu (TW); Tsung-Han Chuang, Tainan (TW); Kai-Lin Chuang, Chia-Yi (TW); Kuo-Cheng Chiang, Zhubei (TW); and Chih-Hao Wang, Baoshan Township, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 3, 2022, as Appl. No. 17/686,139.
Claims priority of provisional application 63/255,129, filed on Oct. 13, 2021.
Prior Publication US 2023/0113269 A1, Apr. 13, 2023
Int. Cl. H10D 30/67 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 30/6757 (2025.01) [H01L 21/0259 (2013.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 62/116 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10D 30/019 (2025.01); H10D 30/435 (2025.01); H10D 62/119 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device structure, comprising:
a plurality of first nanostructures stacked over a substrate in a vertical direction;
a first bottom layer formed adjacent to the plurality of first nanostructures;
a first dielectric liner layer formed over the first bottom layer and adjacent to the plurality of first nanostructures, wherein the first dielectric liner layer covers a sidewall surface of a bottommost first nanostructure; and
a first source/drain (S/D) structure formed over the first dielectric liner layer, wherein the first S/D structure is isolated from the first bottom layer by the first dielectric liner layer.