US 12,336,223 B2
Thin film transistor and display device including the same
Joonseok Park, Yongin-si (KR); Jihun Lim, Yongin-si (KR); Myounghwa Kim, Yongin-si (KR); Taesang Kim, Yongin-si (KR); and Yeonkeon Moon, Yongin-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed by Samsung Display Co., Ltd., Yongin-si (KR)
Filed on Apr. 18, 2022, as Appl. No. 17/722,611.
Application 17/722,611 is a continuation of application No. 16/819,496, filed on Mar. 16, 2020, granted, now 11,309,429.
Application 16/819,496 is a continuation of application No. 16/108,454, filed on Aug. 22, 2018, granted, now 10,593,808, issued on Mar. 17, 2020.
Claims priority of application No. 10-2017-0111930 (KR), filed on Sep. 1, 2017.
Prior Publication US 2022/0238720 A1, Jul. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/67 (2025.01); H01L 23/532 (2006.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 62/80 (2025.01); H10K 59/124 (2023.01)
CPC H10D 30/6755 (2025.01) [H01L 23/5329 (2013.01); H10D 30/6729 (2025.01); H10D 30/673 (2025.01); H10D 30/6757 (2025.01); H10D 62/151 (2025.01); H10D 62/235 (2025.01); H10D 62/80 (2025.01); H10K 59/124 (2023.02)] 22 Claims
OG exemplary drawing
 
1. A thin film transistor, comprising:
an active layer over a substrate and including an oxide semiconductor;
a gate electrode over the active layer and overlapping a channel region of the active layer, the channel region including at least one bent portion as seen in plan view;
a gate line electrically connected with the gate electrode;
a source electrode electrically connected with a source region of the active layer; and
a drain electrode electrically connected with a drain region of the active layer, wherein
a length of a straight line connecting a first contact part connecting the source region and the source electrode and a second contact part connecting the drain region and the drain electrode by a shortest distance is greater than a width of the gate line as seen in plan view, the width of the gate line being the smallest dimension of the gate line as seen in plan view, and
the width of the gate line is parallel to the straight line.