US 12,336,222 B2
Gate-all-around devices with superlattice channel
Shin-Cheng Liu, Hsinchu (TW); and Kuei-Shu Chang Liao, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,776.
Application 18/362,776 is a continuation of application No. 17/459,855, filed on Aug. 27, 2021, granted, now 11,804,532.
Prior Publication US 2024/0021694 A1, Jan. 18, 2024
Int. Cl. H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 30/6735 (2025.01) [H10D 30/6713 (2025.01); H10D 30/6757 (2025.01); H10D 30/797 (2025.01); H10D 62/118 (2025.01); H10D 64/021 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor device, comprising:
forming a superlattice structure extending upward from a semiconductor substrate, wherein the superlattice structure comprises alternating first nanosheets of a first semiconductor material and second nanosheets of a second semiconductor material aligned perpendicular to the semiconductor substrate, the first semiconductor material is different from the second semiconductor material;
forming an insulator layer over the semiconductor substrate, the insulator layer surrounding a bottom portion of the superlattice structure;
forming a gate structure over the insulator layer, the gate structure surrounding a middle portion of the superlattice structure;
depositing a dielectric spacer layer over the gate structure, exposing a top portion of the superlattice structure; and
forming a first doped semiconductor region around the top portion of the superlattice structure.