US 12,336,219 B2
Semiconductor structure and manufacturing method thereof
Yumeng Sun, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on May 12, 2022, as Appl. No. 17/663,185.
Application 17/663,185 is a continuation of application No. PCT/CN2022/076311, filed on Feb. 15, 2022.
Claims priority of application No. 202110775010.2 (CN), filed on Jul. 8, 2021.
Prior Publication US 2023/0010950 A1, Jan. 12, 2023
Int. Cl. H10D 30/63 (2025.01); H10D 30/01 (2025.01); H10D 62/17 (2025.01)
CPC H10D 30/63 (2025.01) [H10D 30/025 (2025.01); H10D 62/292 (2025.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first gate structure on a substrate, a first conductive region and a second conductive region, wherein the first conductive region and the second conductive region are located at two sides of the first gate structure, and in a direction perpendicular to the substrate, the first conductive region and the second conductive region are located at different height positions; and
a second gate structure on the substrate and a third conductive region, wherein the first conductive region and the third conductive region are located at two sides of the second gate structure, and in the direction perpendicular to the substrate, the third conductive region and the first conductive region are located at different height positions; and
wherein the substrate is of a U-shaped structure, a position of the first conductive region on a surface of the substrate is lower than a position of the second conductive region on a surface of the substrate, and the position of the first conductive region on the surface of the substrate is lower than a position of the third conductive region on a surface of the substrate.