| CPC H10D 30/6213 (2025.01) [H10D 30/024 (2025.01); H10D 30/797 (2025.01); H10D 62/116 (2025.01); H10D 62/151 (2025.01); H10D 62/822 (2025.01); H10D 62/832 (2025.01); H10D 62/8325 (2025.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a substrate;
a fin structure,
wherein an upper portion of the fin structures has a surface profile including a top surface of the fin structure having corners with a radius of curvature R, where 0.1 W<R<0.2 W, where W is a width of a channel region in the fin structure;
an isolation region formed over the substrate and in contact with at least a sidewall of the fin structure; and
a gate dielectric layer formed in contact with the fin structure and the top surface of the isolation region, the gate dielectric layer having a thickness that is substantially uniform over the fin structure and the isolation region based on a thermal hydrogen treatment,
wherein:
the gate dielectric layer has a first thickness at the top surface of the isolation region,
the gate dielectric layer has a second thickness at the top surface of the fin structure,
the gate dielectric layer has a third thickness at one or more sidewalls of the fin structure,
the first thickness, second thickness, and third thickness vary from one another by less than 0.3 nanometers, and
the thickness of the gate dielectric layer ranges from 1.8 nm to 5 nm.
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