US 12,336,216 B2
Ferroelectric semiconductor device and method
Chia-Cheng Ho, Hsinchu (TW); Ming-Shiang Lin, Hsinchu (TW); and Jin Cai, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/447,453.
Application 17/874,466 is a division of application No. 16/657,315, filed on Oct. 18, 2019, granted, now 11,522,085.
Application 18/447,453 is a continuation of application No. 17/874,466, filed on Jul. 27, 2022, granted, now 11,855,221.
Prior Publication US 2023/0387310 A1, Nov. 30, 2023
Int. Cl. H10D 30/62 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 64/68 (2025.01)
CPC H10D 30/6211 (2025.01) [H01L 21/02181 (2013.01); H01L 21/02321 (2013.01); H10D 30/024 (2025.01); H10D 64/691 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
an isolation region over a substrate;
a semiconductor fin protruding from a top surface of the isolation region;
a crystalline gate dielectric layer extending along sidewalls and a top surface of the semiconductor fin and along the top surface of the isolation region, the crystalline gate dielectric layer having a crystallization gradient extending along the sidewalls of the semiconductor fin; and
a gate electrode over the crystalline gate dielectric layer.