| CPC H10D 30/6211 (2025.01) [H10D 30/024 (2025.01); H10D 30/6219 (2025.01); H10D 84/013 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01)] | 20 Claims |

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1. A semiconductor device structure, comprising:
a fin structure formed over a substrate;
a gate structure formed over the fin structure;
a first source/drain (S/D) structure formed adjacent to the gate structure;
a first S/D contact structure formed over the first S/D structure;
a first layer formed over the first S/D structure, wherein the first S/D contact structure is surrounded by the first layer, and a portion of the first layer is lower than a bottom surface of the gate structure; and
a dielectric layer formed adjacent to the gate structure and the first layer, wherein the dielectric layer and the first layer are made of different materials, and the first layer is surrounded by the dielectric layer.
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